As the need for bandwidth expands in information and communication networks, bottlenecks develop in the switching hardware due to increases in the number of ports and throughput per port in routing. To handle the increased bandwidth, architectures arose that rely upon increased internal bus widths, increased bandwidths on the busses, and decentralized processing. A block diagram of an example of the architecture of a known router system 100 is shown in FIG. 1. Incoming packets can be temporarily stored in a local buffer 102 until one or more network layer processors, shown as application specific integrated circuits (ASICs) 104 and 106, classifies and determines the forwarding address of the packet. The packets are then routed to the target destination.
Buffer 102 includes gigabytes of SRAM arranged in a very wide data bus (512 bits or more) 108 to allow several simultaneous search operations. Router system 100 analyzes the headers of incoming packets for the appropriate types of operations to be performed on the packet. In the case of TCP/IP route look-up, for example, router system 100 matches a combination of source/destination addresses with entries in a routing table for an exact match or a longest prefix match. Content addressable memory (CAM) 110 offloads ASIC 104 by processing a limited set of lookup instructions. In other applications such as load balancing and URL routing, router system 100 performs more complex search rules and routing data structures.
A successful search will result in router system 100 modifying the header and optionally, the payload, with new information. A packet header may be modified for its output port/queue, output connection, or additional labels for switching, for example. The packets are then queued by priority as well as latency to absorb the time needed to implement the search/modify steps. Output queuing reorders packets in the event multiple packets are searched in parallel.
In the example shown in FIG. 1, data bus 108 is a 640 bit bus with a speed of 133 MHz or 167 MHz. Greater efficiency can be achieved with large data packets, while transfers over data bus 108 are very inefficient for small data packets. ASICS 104 and 106 have a pin count of over 1000 pins. The number of pins cannot be expanded without changing ASICs 104, 106. The bandwidth of router system 100 is therefore limited.
If an ASIC with an expanded number of pins is used, other problems arise which increase production costs and limit scalability of router system 100. For example, the memory interface presents board layout problems, including positioning components to avoid long data bus lines; routing wide data bus lines to memory and processor devices with a large number of pins; and multidrop connections on all busses. Other problems include limited bandwidth per pin, and limited memory access time. Additionally, address fan-out problems arise with increasing address bandwidth and address loading and buffering. Further, noise issues arise with heavy bus loading and heavy bus drivers, line termination, bus contention, and the length of the data bus lines. There are also logistical problems with bus arbitration, transferring small amounts of data on very wide busses, bottlenecks at the memory interface, and bus/clock skew and bit alignment. Numerous memory devices switching on many pins at very high speed also dissipates a large amount of power. Additionally, because increasing bus widths, bus bandwidths, bus loading, ASIC size, and memory depth brings diminishing returns, router system 100 cannot efficiently be expanded to handle greater packet bandwidth.
It is therefore desirable to provide a router that is cost effective and scalable, and alleviates many of the problems listed above.